Various electronic appliances, such as audio-visual appliances, have been recently digitized rapidly. Such electronic appliances are based on specific digital signal processing techniques for converting analog or digital signals into predetermined digital formats, such as MPEG2, to compress the signals, thereby processing the signals at high speeds.
FIG. 13 is a circuit diagram of a conventional digital signal processor 5001. The processor includes a large-scale integrated circuit (LSI) 25, a power supply terminal 26, a power line 27, a decoupling capacitor 28, a DC/DC converter 29, smoothing capacitors 30 and 31, and capacitors 32 for removing noises. The power supply terminal 26 is connected to a direct current (DC) power supply 26A. The power line 27 connects between the power supply terminal 26 and the LSI 25. The decoupling capacitor 28, a solid electrolyte capacitor, is connected between the power line 27 and the ground 5001A. The DC/DC converter 29 connected to the power line 27 converts the voltage of the DC power supply 26A and outputs the converted voltage to the power line 27. The smoothing capacitor 30 is connected between an input port 29A of the DC/DC converter 29 and a ground 5001A while the smoothing capacitor 31 is connected between an output port 29B of the DC/DC converter 29 and the ground 5001A.
As the electronic appliance operates in a high speed, the LSI 25 operates at a high frequency. The LSI 25 operates at a higher frequency, and consumes a more power accordingly. In order to reduce the power consumption of the LSI 25 for reducing heat generated in the LSI 25, the voltage of the DC power supply 26A is decreased to drive the LSI 25 with a low voltage.
Upon being driven with such low voltage, the LSI 25 is influenced easily by a fluctuation of a load. When the amount of the power consumed by the LSI 25 increases rapidly due to the fluctuation of the load, the decoupling capacitor 28 supplies a current to the LSI 25 to stabilize the voltage supplied to the LSI 25.
The decoupling capacitor 28 has an equivalent series resistance (ESR) R and an equivalent series inductance (ESL) L. A current i flows from the decoupling capacitor 28 to the LSI 25. The decoupling capacitor 28 produces a dropping voltage V expressed by the following formula.V=R×i+L×di/dt. That is, upon increasing, the ESR and the ESL prevents a sufficient voltage applied to the LSI 25 from being ensured sufficiently.
FIG. 14 illustrates a profile of a digital noise of the conventional digital signal processor 5001. The digital signal processor 5001 compresses and processes a lot of signals at a high speed, and accordingly, generates a digital noise, as shown in FIG. 14. Particularly being used in a digital television carrier, this digital noise may appear as unstableness of the image on it. In order to reduce the digital noise, a large number of the capacitors 32 are connected between the LSI 25 and the ground 5001A. The number of the capacitors 32 connected to each LSI 25 is not smaller than 30, and further, are necessarily mounted close to the LSI 25. Consequently, the conventional digital signal processor requires a board having the processor mounted thereon to have multiple layers and a large size, accordingly raising its cost.
The digital noise can be evaluated after the digital signal processor has been completed, hence requiring the capacitors 32 to be determined by a cut-and-try procedure. This enables the period of time for dealing with the digital noise to be predicted, and thus, increases the period for its development, accordingly increasing its overall cost.
The ESR and ESL of the solid electrolyte capacitor used as the decoupling capacitor 28 prevent the voltage for driving the LSI 25 to be ensured sufficiently, and need to decrease.